About ICMTS 2013
25-28 March, Osaka University Nakanoshima Center, Japan
The 26th International Conference on Microelectronic Test Structures (ICMTS 2013) will be held at Osaka University Nakanoshima Center, Osaka, Japan, bringing together designers and users of test structures to discuss recent developments and future directions. The conference will be held on March 26-28, 2013, preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on March 25. There will be an equipment exhibition relating to test structure measurements.
2013.01.14
Program details
are available.
2013.01.14
On-line registration page
is open.
Remember!!!Meeting Time
- Tutorial Attendees:
- 25/March from 08:00- at registration desk.
- Conference Attendees
- 25/March (same day as tutorial) 17:00- at registration desk.
Welcome reception (buffet-style dinner with piano music), which is open to everybody, is held at 18:00.
About Osaka and around
Old and new Japan's Economic Capital
Osaka is a city built on an alluvial plain of Yodo River, of which one of the source comes from Biwa-ko Lake, the largest lake of Japan. Due to the excellent accessibility to the sea, Osaka has been an imporatnt trade and exchange seafront as early as 5th century. Around 5th century, although people did not really have writing characters for their daily life, Ookimis, the great Kings, were already capable of constucting Kofuns, their mausoleums. To prove, in Sakai city, which is just on the way from Kansai International Airport to Osaka city center, there are so-many gigantesque mausoleums, including so-called Nintoku-ryo, the largest mausoleum in the world, with his unique keyhole-shape with about 486 meters long 249 meters round-rear and a height of about 35 meters.
Osaka continued to be a capital city of economy of Edo era, from 1603 to 1868. To prove, the starting point of transportation ships were Osaka and the end point was Tokyo; consequently ships from Osaka to Tokyo was called down ships and ships from Tokyo to Osaka was called up ship.
Whilst Samurais in Edo suffered from their lack of money, due to the depletion of gold mines in mid-Edo period (such as in Sado gold mine, which has been the Japan's largest gold mine with 78 tons of gold during his active life. ), Osaka merchant continued to be more and more active. It is believed that revolution of Meiji in 1868 was due to the economic power of Osaka merchants.
In 21st century also, the Osaka habitants continue to be more and more active. The guests of ICMTS 2013 will be able to encounter the Japan's excellent popular foods, histories, traditional (such as Bunraku, puppet operetta) and new (such as Universal Studio Japan) amusements, and suburban natures.
Suggestions for Visitors
(Will come soon. Frequent check of this WEB page is recommended.)
The conference will be held at the
Osaka University Nakanoshima Center, Osaka, Japan on March 25-28, 2013. The Conference center is in the heart of Osaka city. The conference will start with a one-day Tutorial Short Course on Microelectronic Test Structures. There will be an equipment exhibition relating to test structure measurements.
Original papers presenting new developments in silicon, III-V compounds, and nanotechnology microelectronics test structure research, implementation, and applications as well as test structures aimed at new materials and devices characterization are solicited.
Suggested topics include (but are not limited to):
Material and Process Characterization:
Evaluation of wafer start materials (Si, SiGe, strained
silicon, SOI, III-V, II-VI, etc.), dielectrics (high-k gate, low-k interconnect), homoepitaxial and
heteroepitaxial layers. Resistivity, mobility, stress, contact resistance, dielectric, and interconnect
measurements.
Replicated Feature Metrology:
Electrical and non-electrical characterization of level-to-level
registration, feature placement, critical dimension, mask and reticle process control.
Manufacturing of Integrated Circuits and MEMS:
Evaluation of individual and groups of integrated circuits, device and MEMS process steps and elements: transistors, diodes, mechanical
structures, device isolation, memory cells and interconnect. Assessment of MMICs, RF components,
3D integration and multi chip packages.
MEMS, NEMS, and Microfluidics:
Test structures and methods for evaluating electro-mechanical
devices, such as actuators, sensors, switches, and microfluidic devices.
Large Area Electronics and Emerging Devices:
Test structures for evaluating displays, printed /
flexible devices, power devices, photovoltaics, as well as emerging devices, such as organic /
oxide-based / biomolecular / spintronic devices, ReRAMs, nano-structures, and related materials.
Device and Circuit Modeling, Parameter Extraction: Model parameter extraction, RF device
modeling, de-embedding, pulsed measurements, DC / AC / high frequency measurement techniques
and applications.
Reliability Test Structures:
Test structures and methods for transistor / thin film / dielectric /
interconnect reliability evaluation, quality assurance, thermal monitoring and analysis, accelerated
wafer level tests, wafer level burn-in, and reliability prediction.
Matching and Variability Test Structures:
Mismatch / variability characterization and modeling
of components (transistors, resistors, capacitors, inductors, mechanical components) and circuits.
Technology R&D, Integration, and DFM:
Test structures for FEOL or BEOL evaluation, design
rule determination, process uniformity and worst-case analysis, assessment of integration and new
technologies. Calibration of DFM models such as lithography, OPC, CMP, or parametric variation.
Evaluation and optimization of standard cell macros and other product circuits.
Yield Enhancement and Production Process Control:
Yield enhancement structures and methods,
yield modeling, statistical process control, defect estimation structures and methods, failure
identification and characterization, many-component / matrix test circuitry for technology assessment,
evaluation of design-manufacturing interactions (DFY).
Test Structure Design Methods:
Design flows for automated design, verification strategies, design
for analysis, parameterized design, and related design issues.
Test Structure Utilization Strategy:
Test equipment, probing and programmable testing for process
diagnostics, test throughput optimization, database and data analysis methods, statistical data
analysis, expert systems, and related techniques.
Organized by:
- The IEEE Electron Devices Society
- Association for Promotion of Electrical, Electronic and Information Engineering
In cooperation with:
- The Institute of Electronics, Information and Communication Engineers, Electronics Society
- The Japan Society of Applied Physics
Copyright (c) Tsuyoshi SEKITANI and Yoshio MITA all rights reserved
icmts2013 at if.t.u-tokyo.ac.jpVersion of this document: $Id$ 