Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration Hotel Registration

Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Tutorial (March 18)

08:30 Registration
09:00 Welcome
09:10 Ryoichi Nakamura: 3D integration technology for CMOS image sensors and future prospects

Abstract:

3D integration is core technology for advanced devices. CMOS image sensor(CIS) uses 3D integration technology most effectively and has remarkably progressed for these years. In order to realize higher sensitivity and multi-functionality, many types of back-illuminated(BI) stacked CISs are currently in mass production. This talk will focus on recent progress of 3D integration technology used in CIS devices, including
(1)Technology of stacked CIS and evaluation (TSV, Cu-Cu bonding, etc.)
(2) Advantages and use case of stacked CIS, and (3)Future prospects of CIS devices.

Biography:

Ryoichi Nakamura received the B.S., and M.S. degrees from Tokyo Institute of Technology in 1994 and 1996 respectively. He has been working on DRAM, SRAM, CMOS device and process development. He is currently involved in Research Division of Sony Semiconductor Solutions Corporation, and recently he is engaging himself in the 3D stacked CMOS image sensor development.
10:00 Coffee Break
10:20 Yuichiro Mitani: 3D NAND Flash Memory - Electrical and Physical characterizations for Memory Cell Reliability

Abstract:

As conventional planer NAND flash memories are limited from physical and electrical scaling point of view, the three-dimensional NAND (3D-NAND) flash memories, in which memory cells are stacked vertically, has rapidly achieved maturity to keep a trend of increasing bit density and reducing bit cost. To realize more capacity, total number of layers are increasing (>64 layers) and multi-level cell (MLC) operations are indispensable (>3bit/cell). Extending this capacity trend requires highly-reliable memory cell. This talk will focus on the typical charge-trap type memory cell, and the electrical and physical characterization of tunnel oxide, charge trap film, and poly-Si channel will discuss from the viewpoint of understanding reliability mechanisms.

Biography:

Yuichiro Mitani received the B. E. and M. E. in material science and engineering from Tohoku University, Sendai, Japan, in 1990 and 1992, respectively. He received the Ph.D. from The University of Tokyo in 2009. He joined the R&D Center, Toshiba Corporation in 1992. His primary works were in the Si-CVD and the ultra-shallow junction process technology. Since 1999, he has been with the Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, and he engaged the research of the reliability mechanisms for CMOS and flash memory devices. Now, he is a chief specialist at the Device Technology Research & Development Center, Toshiba Memory Corporation. His research interests include characterization and process engineering of CMOS and nonvolatile memory devices, and device reliability.
11:20 Ichiro Omura: Power Semiconductor Device Basics

Abstract:

This tutorial include six topics related to Power semiconductor devices: (1) History of power semiconductor devices, (2) Power electronics circuit principle and major applications of power semiconductors, (3)Power semiconductor device structures and physics, (3-1) Power MOSFET / Superjunction MOSFET, (3-2) IGBT, (3-3)Power diodes (PiN diode and SBD), (3-4)Lateral devices (LD-MOS, LIGBT) for power integrated circuits, (3-5)Thyristors (GTO, GCT) for Giga watt applications, (4)Status and future possibility of SiC, GaN power devices, (5)Protection, packaging and reliability of power semiconductors, (6)Other topics.

Biography:

Ichiro Omura (Member, IEEE) received his M.S. degree from Osaka University, Osaka in 1987 and Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich in 2001. From 1987 he had been with Toshiba Corporation, Kawasaki, Japan, engaging in research on power semiconductors including high voltage IGBTs, super-junction MOSFETs and GaN power devices. From 1996 to 1997, he was a visiting Researcher at ETH. Since 2008, he has been with the Kyushu Institute of Technology, Japan. He has published papers over 80 journals and conference papers, has filed more than 140 patent applications and holds more than 40 patents in the field of power semiconductors. He has been the director of next generation power electronics research center in Kyushu Institute of Technology since 2012. His research interests are new power semiconductor device design, reliability testing with new monitoring system and advanced digital gate drive technology.
12:20 Lunch
13:40 Stewart Smith: Microelectronic Test Structure Fundamentals

Abstract:

This presentation will begin with a review of test structures detailing their history and hot topics over the past 30 years. The presentation will include the development of test structures for measuring sheet resistance, line width and contact resistance. Measurement issues associated with test structure and pad layout, along with developments in probe technologies will also be explored.

Biography:

Stewart Smith received the B. Eng. (Hons) degree in Electronics and Electrical Engineering in 1997 and the Ph.D. degree in 2003 from the University of Edinburgh, Scotland, UK. He has published papers at every ICMTS conference from 1999 onwards and received the best paper award at ICMTS 2004 (Awaji, Japan). Stewart is a Lecturer in Electronics with the School of Engineering at the University of Edinburgh. His research interests include the design and fabrication of biological and medical microsystems, integration of novel technologies with CMOS and test structures for microsystem fabrication processes.
14:40 Bill Verzi: The Fundamentals of Measurement Theory

Abstract:

The sciences have always depended on experimentation for the proof that testing has given to the scientist. It is with experimental test that science advances. This discussion will highlight interesting aspects of experimental testing that have laid the foundation for modern scientific inquiry. We will see that much of what we do today to evaluate the semiconductor process has foundations in science discovered hundreds of years ago. From the beginnings of physical measurements in time to the advances in construction of experimental devices, we will see that knowledge and understanding have greatly advanced. After considering the fundamentals of test structures, this discussion will emphasize fundamentals of measurement technique, giving the student a solid foundation for reliable measurements. The search for new materials and devices required to drive progress in semiconductor device performance push the boundaries of electronic measurement capability. While we cannot deny the laws of physics, we can improve the ability to observe. What are the metrics for this improvement? How does precision, repeatability, and speed of execution affect our ability to observe? How does the knowledge of the limits of measurement help us? We shall discuss these issues and explore the limits of measurement capability in this discussion.

Biography:

Bill Verzi (IEEE Member 1986) received a degree from West Valley College, Saratoga, CA, in 1981, supplemented with additional study at San Jose State University, San Jose, CA. He joined Intel in 1978 where he was involved in the quality assurance of memories, working in the California Technology Development group from 1979 to support the development of static/logic semiconductor processes. At Intel he was responsible for front end device characterization, test structure design, and test system development. He joined Hewlett Packard in 1988 as an applications engineer. He accepted an assignment to SEMATECH in 1990, where he designed and supported electrical test methods for process characterization with a focus on plasma damage evaluation. Now with Keysight Technologies, his focus continues to be the evaluation of the semiconductor process. He has served on the technical committee of ICMTS since 1998. He is a JEDEC committee member.  He was Technical Chair for ICMTS 2003 and General Chair for ICMTS 2006.  He now serves as the chairman of the steering committee of ICMTS.
15:40 Coffee Break
16:00 Colin McAndrew: Modeling Methods Fundamentals, and Why What You Learned in School About Transistor Capacitances is Wrong!

Abstract:

This tutorial will address two aspects of modeling: fundamentals of how to develop good models; and why the small-signal model for transistors (MOS and BJT) presented in every design textbook, and taught in all EE design classes, is wrong. We will start by reviewing how SPICE works, then show how this defines the best way to formulate models and how to get SPICE to solve equations, both algebraic and differential, for you “inside” your model. Fundamental model requirements, and benchmarks to verify if your model meets these requirements, will be reviewed. The four basic formulation approaches for MOS transistor models will be detailed. Do you know what the difference is between Cdg and Cgd? Which is more important in analog design? Are they Miller-multiplied, like we were taught as undergraduates, or not? Why are Csd and Cds negative? Did you know that even the gm and go in text-book representations of the hybrid-p model are wrong? This tutorial will answer those questions and will also present a new small-signal representation, not (yet) in text books, that gives the most intuitive and useful of the 11,440 possible small-signal model topologies for 4-terminal devices.

Biography:

Colin McAndrew: received the Ph.D. degree in systems design engineering from the University of Waterloo, Canada. He was at AT&T Bell Laboratories for 7 years, and since 1995 has been with NXP (formerly Freescale) in Arizona, where he is a Fellow of Technical Staff. He is a Fellow of the IEEE, was an editor of the IEEE Transactions on Electron Devices from 2001 to 2010, and has been an editor of the IEEE Journal of the Electron Devices Society since 2013. He is or has been on the technical program committees for the IEEE BCTM, ICMTS, CICC, and BMAS conferences. He received best paper awards from ICMTS in 1993 and 2012, CICC in 2002, and BCTM in 2015. He has published more than 130 refereed journal and conference papers, 10 book chapters, and one book, and given numerous invited papers and short courses at leading industry conferences. His works is primarily on compact and statistical modeling of semiconductor devices.
17:00 Toru Nakura: Power Supply Noise Suppression and Emulation to Improve Reliability of LSI operations

Abstract:

This tutorial discusses power supply noise on LSIs. First we discuss causes and effects of power supply noise. We show that the power supply impedance and rush current at the mode switching of an LSI are the main causes of the power supply noise. Next we introduce some methods to suppress the power supply noise by using passive devices or active circuits. Then we introduce power supply impedance emulation techniques to eliminate overkills and underkills at volume production pre-shipping test. To understand and control the power supply noise are one of the keys to enhace the reliability of LSI operations.

Biography:

Toru Nakura received the B. S., M. S. and Ph.D degree in electronic engineering from The University of Tokyo in 1995, 1997 and 2005 respectively. He worked in the industry as a circuit designer as well as an EDA tool developer. He joined the University of Tokyo again as an associate professor at VLSI Design and Education Center (VDEC), and Electrical Engineering and Information Systems, in The University of Tokyo. He is now currently working as an full professor in the department of Electronics Engineering and Computer Science in Fukuoka University. His current interest includes signal integrity, reliability, power supply, digitally-assist analog circuits, and fully automated analog circuit synthesis.
18:00 Closing
18:05 Reception